대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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- Pages.1512-1515
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- 1987
최소 delay를 갖는 buffer 회로의 설계
A Design of The Buffer Circuit having Minimum Delay Time
- Kang, In-Yup (Dept. of Electronics Engineering Seoul National University) ;
- Song, Min-Kyu (Dept. of Electronics Engineering Seoul National University) ;
- Kim, Won-Chan (Dept. of Electronics Engineering Seoul National University)
- 발행 : 1987.07.03
초록
The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.
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