Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07b
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- Pages.1507-1511
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- 1987
Design of Easily Testable CMOS Sequential PLAs
테스트가 용이한 CMOS 순서 PLA의 설계
Abstract
This paper proposes a NAND-NAND logic sequential Programmable Logic Array (PLA) using CMOS technology, and test generation methods about stuck-open faults. By using LSSD (Level Sensitive Scan Design) method instead of Flip-Flops in Sequential PLA, the complex test problems of sequential logic are simplified. After generating the test sets using connection graph, regular test sequences and all transistor faults detection method in PLA are proposed. Finally, by programming these algorithms in PASCAL at VAX 8700 and adopting these to pratical CMOS Sequential PLA circuits, we proved the effectiveness of this design.
Keywords