Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07b
- /
- Pages.1488-1491
- /
- 1987
Design of FFT processor with systolic architecture
시스토릭 아키텍쳐를 갖는 FFT 프로세서의 설계
- Kang, B.H. (Dept. of Electronics Eng., Yonsei Univ.) ;
- Jeong, S.W. (Dept. of Electronics Eng., Yonsei Univ.) ;
- Lee, J.K. (Dept. of Electronics Eng., Yonsei Univ.) ;
- Choi, B.Y. (Dept. of Electronics Eng., Yonsei Univ.) ;
- Shin, K.W. (Dept. of Electronics Eng., Yonsei Univ.) ;
-
Lee, M.K.
(Dept. of Electronics Eng., Yonsei Univ.)
- 강병훈 (연세대학교 전자 공학과) ;
- 정성욱 (연세대학교 전자 공학과) ;
- 이장규 (연세대학교 전자 공학과) ;
- 최병윤 (연세대학교 전자 공학과) ;
- 신경욱 (연세대학교 전자 공학과) ;
-
이문기
(연세대학교 전자 공학과)
- Published : 1987.07.03
Abstract
This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].
Keywords