Functional Simulation of Logic Circuits by Prolog

Prolog를 이용한 논리회로의 기능적 시뮬레이션

This paper proposes a functional simulation algorithm which decrease the internal memory space and run time in simulation of VLSI. Flip-flop, register, ram, rom, ic and fun are described as functional elements in the simulator. Especially icf is made as new functional element by combining the gate and the functional element, therefore icf is used efficiently in simulation of VLSI. The proposed algorithm is implemented on PC-AT(MS-DOS) in by Prolog-1.