다중 프로세서 전전자 교환기의 구조 및 성능분석

Architecture and performance analysis of multiprocessor ESS

This paper proposes analytic models of the large scale ESS's control system which has the multiprocessor architecture. The performance indices such as the ringback tone delay, busy tone delay, queue length and processor idletime are investigated through the analytic model. The system bottleneck is also analyzed. For the validation of analytic models, its simulation is performed using the SDL/SIM package for the case of 100,000 subscribers. From computer simulation, the results of analytic models are shown to be similar to the results of simulation models, which validates the analytic models.