Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Architecture and performance analysis of multiprocessor ESS

다중 프로세서 전전자 교환기의 구조 및 성능분석

  • Park, Heon-Chul (Dept. of Control and Instrumentation Eng., Seoul National Univ.) ;
  • Kwon, Wook-Hyun (Dept. of Control and Instrumentation Eng., Seoul National Univ.)
  • 박헌철 (서울대학교 공과대학 제어계측과) ;
  • 권욱현 (서울대학교 공과대학 제어계측과)
  • Published : 1987.07.03
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Abstract

This paper proposes analytic models of the large scale ESS's control system which has the multiprocessor architecture. The performance indices such as the ringback tone delay, busy tone delay, queue length and processor idletime are investigated through the analytic model. The system bottleneck is also analyzed. For the validation of analytic models, its simulation is performed using the SDL/SIM package for the case of 100,000 subscribers. From computer simulation, the results of analytic models are shown to be similar to the results of simulation models, which validates the analytic models.

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