한국통신학회:학술대회논문집 (Proceedings of the Korean Institute of Communication Sciences Conference)
- 한국통신학회 1986년도 춘계학술발표회 논문집
- /
- Pages.177-180
- /
- 1986
RADIX-2 BUTTERFLY 연산회로의 설계
초록
A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.
키워드